This invention relates to a semiconductor memory device; and, more particularly, to a memory device which is capable of distributing load of input/output lines and thus capable of operating in a high speed.
Recently, there have been developed high-speed semiconductor memory devices. These memories are provided with a clock signal having small period for operations. The small clock signal is needed to provide high-speed operations.
FIG. 1 is a block diagram illustrating a structure of a memory device, which shows four memory banks for illustration. As shown, a global read line GRIO and a global write line GWIO are connected to four sense amplifiers 2 and four write drivers 3 in each of the four memory banks 10, respectively.
On a read operation, the data output through the global read line GRIO is provided to outside through three multiplexers MUX1 to MUX3. Initially or in standby state, the global read line GRIO is pre-charged to a high level by a global read line pre-charge unit 20. In this case the global read line GRIO is shared by 16 sense amplifiers 2 and 3 multiplexers MUX1 to MUX3, thereby applying a very big line load to the global read line GRIO.
On the read operation, only one sense amplifier among 16 sense amplifiers 2 operates and a big line load is applied to the operating sense amplifier. Thus, the output data from the operating sense amplifier is a skewed signal having a small slope, which requires a clock signal with a large period to differentiate the output signals, thereby reducing operation speed.
There is disclosed to overcome this problem by increasing driver capability of the sense amplifiers 2 but this approach increases power consumption therein.
On the other hand, on a write operation the data inputted to a data input multiplexer DIMUX is written to a memory cell by a write driver among 4 write drivers in a memory bank. In this case the global write line GWIO is shared by 16 write drivers 3 and one data input multiplexer DIMUX, and thus very big line load is applied to the global write line GWIO. The same problems as in the read operation are occurred. That is, employing clock signal with small slope reduces operation speed, and increasing driver capability of the write driver 3 increases power consumption therein.
It is, therefore, an object of the present invention to provide a semiconductor memory device, which is capable of distributing load of input and output lines and thus capable of operating in a high speed.
In accordance with an aspect of the present invention, there is provided a semiconductor memory device for distributing load of input and output lines, comprising: a line pre-charging means for pre-charging a global read line composed of a pair of lines to a high level in an initial or steady state; a plurality of memory banks connected to a global write line composed of a pair of lines for storing data provided thereto, each of which includes a memory cell array composed of a number of memory cells coupled to a multiplicity of sense amplifiers and the multiplicity of write drivers, wherein said multiplicity of amplifiers amplifies data signals from the memory cells to provide it through a read line composed of a pair of lines to a read line driver which provides the data on said read line to said global read line on a read operation, and said multiplicity of write drivers are connected through a write line composed of a pair of lines to said write line driver for storing the data on said global write line into the memory cells; a number of multiplexers for selecting the data from said read line; and a data input means for providing externally inputted data to said global write line on the write operation.